Creating Test Sequences for RISC-V Cores and SoCs

Louie De Luna | Agnisys Chief Product Evangelist
Creating Test Sequences for RISC-V Cores and SoCs

The idea of an open-source CPU core was virtually unheard-of ten years ago – let alone using it for commercial applications. The CPU core has been the most critical part of any computing system and thus, has been the most valuable and profitable. Over the years, companies like IBM®, Intel® and ARM® have built their empires either from CPU core development or license distribution.

Fast forward to today, the entire computing industry is in the early stages of a new paradigm shift where the CPU would no longer be the central processing unit. Mainly driven by the exploding growth of data that we produce and consume as a global society, even the highly successful von Neumann architecture is becoming obsolete. There is big data used for prediction, analytics and machine learning training, and there is fast data used for real-time applications such as IoT edge, geo-spatial systems and autonomous vehicles.

As we prepare for the future, data would need to be at the center stage. The computing architecture would need to be data-centric rather than CPU-centric. The CPU would only be one of the types of hardware along with GPUs, FPGAs, custom accelerators, special-purpose CPUs, memory and storage, all connected to an open-source interface and all are powered by an open-source Instruction Set Architecture (ISA). The ISA that is poised to be the key enabler for all of this is RISC-V. Ever since the group at UC Berkeley completed RISC-V and released it as open-source in 2014, the game started to change. Learning from the success of the Linux Foundation, RISC-V Foundation was also started in 2015, and now comprises of 325 members organizations ensuring that the world’s first open ISA will prove to be useful towards mass adoption.

SweRV Core 1Western Digital Corporation (WDC), one of the founding leaders of the RISC-V Foundation (and also one of our customers), released a commercial-grade open-source CPU core based on RISC-V called SweRV™, a 32-bit CPU that supports RISC-V integer, compressed instruction, multiplication and division, and instruction-fetch fence and CSR instructions extensions. The core is a 9-stage, dual-issue, superscalar pipeline. SweRV delivers about 4.9 Coremark/MHz, in-between Intel Xeon™ E5 at ~5.5 Coremark/MHz and ARM Cortex™ A15 at ~4.7 Coremark/MHz.

Read the full blog post here

Published on 17/10/2019