Breker Verification Systems Unveils System Coherency Synthesis TrekApp Building on Its Successful Cache Coherency Test Solution

System Coherency Synthesis TrekApp Generates High Coverage Tests to Stress Coherency, Detect Corner Cases for Range of SoC Platforms, Processors.

published in Verification Services on 06/12/2021

SAN JOSE, CALIF. - December 6, 2021 - Breker Verification Systems today unveiled its System Coherency Synthesis TrekApp used to generate thousands of high-coverage tests to stress cross-system coherency for a broad range of SoC platforms and processors.

Based on Breker’s Cache Coherency TrekApp, the System Coherency Synthesis TrekApp uses abstract models of common and novel algorithms to automatically generate coherency test content for complex, multi-agent system platforms based on coverage directives. The TrekApp can be configured for Arm, RISC-V and other processor configurations and broad range of storage and I/O architectures.
“System coherency is an increasingly complex and error-prone challenge for many SoC platforms that requires considerable expertise and effort to accomplish,” says Adnan Hamid Breker’s executive president and CTO. “Our Test Suite Synthesis technology produces dramatic improvements in test composition time and coverage over manual tests and basic test generators including templating schemes.”

Breker, the leading provider of advanced test content synthesis solutions for SoC, UVM and Post-Silicon verification environments, will demonstrate its System Coherency Synthesis TrekApp and other solutions at Design Automation Conference (DAC) in Booth #2528. DAC will be held Monday, December 6, through Wednesday, December 8, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

Introducing the System Coherency Synthesis TrekApp

The increase in SoC complexity and diverse processor architectures makes coherency a challenge that cannot be ignored in semiconductor development projects. Breker’s next-generation TrekApp uses its Test Suite Synthesis technology to address coherency across the entire system to include fabric and I/O issues as well as advanced memory architectures more effectively than zero abstraction templating and similar schemes. 

The TrekApp leverages established methods such as the Dekker algorithm, the Moesi state protocol for system-wide testing, stride testing, false sharing analysis and other exclusive test mechanisms.
Coupled with a range of processor integration tests for Arm v8/v9 and the RISC-V Instruction Set Architecture (ISA) the TrekApp generates comprehensive test content for most SoCs in development today. Specialized custom instructions or even complete instruction sets can be included, and alternative test algorithms can be inserted, crossing test content output results for high verification coverage.

The System Coherency TrekApp generates C code and transactions for system-level testbenches or UVM sequences for cache unit and sub-system simulation. It operates on virtual prototype platforms, simulation, emulation, FPGA prototyping or final silicon, and enables the full debug and profiling of the device under test on those platforms.

The System Coherency Synthesis TrekApp is a component of the Breker TrekApp solution library that provides automated test content for a variety of SoC scenarios, including cache coherency, Arm and RISC-V integration, power domain management, security and network traffic generation. TrekApps operate on the Breker Test Suite Synthesis Solution and Synthesizable VerificationOS for automated, coverage-driven test generation for a variety of multi-threaded platforms from a single, easy-to-understand specification model.

Availability and Pricing

System Coherency Synthesis TrekApp is available and in use on multiple development projects. 
Pricing is available upon request.
    For more information, email [email protected]