Using SmartSpice Compact Models
This webinar will provide a guide to developing Compact Models in SmartSpice to achieve optimal simulation performance. You will learn how models are used in SmartSpice and best practices when constructing a custom Verilog-A model. You will also learn about built-in simulator models versus custom Verilog-A models and how to look at the circuit simulation results to debug your model. This will lead to a better understanding of SmartSpice to get good simulations and allow you to explore circuit behavior. Examples and templates, available online, will also be introduced to help meet general simulation requirements.